1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit device such as an IC (Integrated Circuit) and an LSI (Large Scale Integrated Circuit), and more particularly to a semiconductor integrated circuit device having an ESD (Electrostatic Discharge) protection circuit for protecting an internal circuit from ESD.
2. Description of the Related Art
If ESD occurs, for example, while a semiconductor integrated circuit device is being conveyed by a machine, a high voltage of, e.g. about several-hundred V to several-thousand V is applied to the semiconductor integrated circuit device in a very short time. This may lead to destruction of an internal circuit (semiconductor integrated circuit). In order to protect the semiconductor integrated circuit device such as an IC or an LSI from ESD, a variety of ESD protection circuits have been proposed (see, for instance, Jpn. Pat. Appln. KOKAI Publication No. 7-240510, U.S. Pat. No. 6,249,414, and EOS/ESD SYMPOSIUM 2001, 1A.3 “GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes”). An ESD protection circuit is provided in the semiconductor integrated circuit device, thereby to release a high voltage, which is applied to the internal circuit due to ESD, and to protect the internal circuit from destruction.
Referring to FIG. 1 and FIG. 2, a prior-art ESD protection circuit is described.
FIG. 1 is a circuit diagram depicting the prior-art ESD protection circuit. As is shown in FIG. 1, a pad 11 and a pad 12 are connected to an internal circuit 10 that is to be protected. The ESD protection circuit comprises a thyristor (SCR) circuit 13 for releasing an excessive ESD current, and a control circuit 15 that controls the on/off of the thyristor circuit 13.
The thyristor circuit 13 has an anode connected to the pad 11 and a cathode connected to the pad 12. The thyristor circuit 13 comprises a PNP bipolar transistor 16, an NPN bipolar transistor 17 and a resistor element 18. The PNP bipolar transistor 16 has an emitter connected to the pad 11, a base connected to a collector of the NPN bipolar transistor 17, and a collector connected to the control circuit 15. The NPN bipolar transistor 17 has a base connected to the control circuit 15, and an emitter connected to the pad 12. The resistor element 18 has one end connected to the control circuit 15, and the other end connected to the pad 12.
The control circuit 15 comprises a GG (Gate Grounded) NMOS transistor 19 and a resistor element 20. The GGNMOS transistor 19 has a drain connected to the pad 11, and a gate and a source both connected to the thyristor circuit 13. The resistor element 20 has one end connected to the gate and source of the NMOS transistor 19, and the other end connected to the pad 12.
The operation of the prior-art ESD protection circuit will now be described referring to FIG. 2. FIG. 2 is a graph showing voltage/current characteristics of the GGNMOS transistor 19 shown in FIG. 1. The abscissa in FIG. 2 indicates a voltage V1 that is applied between the drain of the GGNMOS transistor 19, on the one hand, and the source and gate of the GGNMOS transistor 19, on the other hand. The ordinate indicates a current I1 that flows between the drain and the source and gate of the GGNMOS transistor 19 and flows through the thyristor circuit 13.
If a high voltage due to ESD is applied between the pad 11 and pad 12, the high voltage due to ESD is applied to the drain of the GGNMOS 19. Then, as shown in FIG. 2, after the voltage reaches a trigger voltage Vt1, it drops to a hold voltage Vh due to a snap-back characteristic. Thereafter, breakdown occurs between the drain of the GGNMOS transistor 19 and the substrate, and a parasitic NPN bipolar transistor of the GGNMOS transistor 19 operates and a current flows with a sharp increase. Consequently, a base current flows to the base of the NPN bipolar transistor 17 of thyristor circuit 13, thereby turning on the thyristor circuit 13 and a large current due to ESD flows between the anode and cathode of the thyristor circuit 13. By this operation, the ESD voltage applied between the pad 11 and pad 12 is released through the thyristor circuit 13. Therefore, the ESD voltage is not applied to the internal circuit 10, and the internal circuit 10 is protected.
As is shown in FIG. 2, in order to cause a large current to flow through the thyristor current 13, a sufficiently large current needs to be made to flow before the voltage V1 exceeds a gate breakdown voltage Vg of the internal circuit. However, with present-day miniaturization of an LSI, etc., which constitutes the internal circuit 10, the thickness of the gate oxide film of the MOS transistor in the LSI has decreased more and more. Consequently, the gate breakdown voltage Vg has decreased more and more.
Since the thyristor 13 comprises the PNP bipolar transistor 16 and NPN bipolar transistor 17, the value of on-state resistance is high. As a result, before a large current is let to flow, the voltage V1 exceeds the gate breakdown voltage Vg. Moreover, in order to cause a sufficient current to flow before the voltage V1 exceeds the gate breakdown voltage Vg, it is necessary to increase the size of each bipolar transistor 16, 17 and to decrease the on-state resistance. This, however, leads to an increase in chip size and a rise in manufacturing cost.